Implementing electronic circuits involves connecting isolated devices through specific electronic paths. In silicon integrated circuit fabrication it is necessary to isolate devices from one another which are built into the same silicon matrix. They are subsequently interconnected to create the desired circuit configuration. In the continuing trend toward higher device densities, parasitic interdevice currents become more problematic, thus isolation technology has become one of the most critical aspects of contemporary integrated circuit fabrication.
Over the last few decades a variety of successful isolation technologies have been developed to address the requirements of different integrated circuit types such as NMOS, CMOS and bipolar. In general, the various isolation technologies exhibit different attributes with respect to such characteristics as minimum isolation spacing, surface planarity, process complexity and defect density generated during isolation processing. Moreover, it is common to trade off some of these characteristics when developing an isolation process for a particular integrated circuit application.
In metal-oxide-semiconductor (MOS) technology it is necessary to provide an isolation structure that prevents parasitic channel formation between adjacent devices, such devices being primarily NMOS or PMOS transistors or CMOS circuits. The most widely used isolation technology for MOS circuits has been that of LOCOS isolation, an acronym for LOCal Oxidation of Silicon. LOCOS isolation essentially involves the growth of a recessed or semirecessed oxide in unmasked non-active or field regions of the silicon substrate. This so-called field oxide is generally grown thick enough to lower any parasitic capacitance occurring over these regions, but not so thick as to cause step coverage problems. The great success of LOCOS isolation technology is to a large extent attributed to its inherent simplicity in MOS process integration, cost effectiveness and adaptability.
In spite of its success, several limitations of LOCOS technology have driven the development of alternative isolation structures. A well-known limitation in LOCOS isolation is that of oxide undergrowth at the edge of the mask which defines the active regions of the substrate. This so-called bird's beak (as it appears) poses a limitation to device density, since that portion of the oxide adversely influences device performance while not significantly contributing to device isolation. Another problem associated with the LOCOS process is the resulting circuit planarity or lack thereof. For submicron devices, planarity becomes an important issue, often posing problems with subsequent layer conformality and photolithography.
Trench isolation technology has been developed in part to overcome the aforementioned limitations of LOCOS isolation for submicron devices. Refilled trench structures essentially comprise a recess formed in the silicon substrate which is refilled with a dielectric material. Such structures are fabricated by first forming submicron-sized trenches in the silicon substrate, usually by a dry anisotropic etching process. The resulting trenches typically display a steep sidewall profile as compared to LOCOS oxidation. The trenches are subsequently refilled with a dielectric such as chemical vapor deposited (CVD) silicon dioxide (SiO2). They are then planarized by an etchback process so that the dielectric remains only in the trench, its top surface level with that of the silicon substrate. The etchback process is often performed by etching photoresist and the deposited silicon dioxide at the same rate. The top surface of the resist layer is highly planarized prior to etchback through application of two layers of resist, and flowing the first of these layers. Active regions wherein devices are fabricated are those that were protected from etch when the trenches were created. The resulting structure functions as a device isolator having excellent planarity and potentially high aspect ratio beneficial for device isolation. Refilled trench isolation can take a variety of forms depending upon the specific application; they are generally categorized in terms of the trench dimensions: shallow trenches (<1 μm), moderate depth trenches (1–3 μm), and deep, narrow trenches (>3 μm deep, <2 μm wide). Shallow Trench Isolation (STI) is used primarily for isolating devices of the same type and is often considered an alternative to LOCOS isolation. Shallow trench isolation has the advantages of eliminating the birds beak of LOCOS and providing a high degree of surface planarity.
The basic trench isolation process is, however, subject to drawbacks, one of these being void formation in the trench during dielectric refill. Such voids are formed when the refilling dielectric material forms a constriction near the top of a trench, preventing flow of the material into the trench interior. Such voids compromise device isolation as well as the overall structural integrity. Unfortunately, preventing void formation during trench refill often places minimum size constraints on the trenches themselves, which may compromise device packing density or device isolation. For example, a key parameter measuring device isolation is the field threshold voltage between adjacent devices, that is, the voltage necessary to create a parasitic channel beneath a field oxide region linking adjacent devices. The field threshold voltage is influenced by a number of physical and material properties of the trench isolator such as insulator thickness, dielectric constant ε, substrate doping, field implant dose and substrate bias. Thus, a principal difficulty in decreasing the trench depth is the compromise in device isolation. Clearly, it is highly desirably to develop a shallow trench isolation process which overcomes the problem of void formation while providing effective device isolation.